entity easy is port ( a,b: in bit; q: out bit ); end easy; architecture easy_arch of easy is begin q<=a XOR b; end; use WORK.easy; entity tb is end tb; architecture tb_arch of tb is signal tb_a,tb_b: bit; signal tb_q: bit; component easy port ( a,b: in bit; q: out bit ); end component; begin E0: easy port map(a=>tb_a,b=>tb_b,q=>tb_q); tb_a<='0' after 10 ns,'1' after 20 ns,'0' after 30 ns,'1' after 40 ns,'0' after 50 ns; tb_b<='0' after 10 ns,'0' after 20 ns,'1' after 30 ns,'1' after 40 ns,'0' after 50 ns; end;