library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity ramcell is port ( din: in std_logic_vector(15 downto 0); dout: out std_logic_vector(15 downto 0); addr: in std_logic_vector(7 downto 0); ce: in std_logic; rst_n: in std_logic; clk: in std_logic ); end entity; architecture ramcell_arch of ramcell is type mem is array(0 to 255) of std_logic_vector(15 downto 0); signal memory: mem; begin process (clk,rst_n) begin if (rst_n='0') then for i in 0 to 255 loop memory(i)<=(others=>'0'); end loop; dout<=(others=>'0'); elsif (clk'event and clk='1') then if (ce='1') then memory(conv_integer(addr))<=din; end if; dout<=memory(conv_integer(addr)); end if; end process; end architecture; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use WORK.ramcell; entity tb is end entity; architecture tb_arch of tb is signal tb_din: std_logic_vector(15 downto 0); signal tb_dout: std_logic_vector(15 downto 0); signal tb_addr: std_logic_vector(7 downto 0); signal tb_ce: std_logic; signal tb_rst_n: std_logic; signal tb_clk: std_logic; component ramcell is port ( din: in std_logic_vector(15 downto 0); dout: out std_logic_vector(15 downto 0); addr: in std_logic_vector(7 downto 0); ce: in std_logic; rst_n: in std_logic; clk: in std_logic ); end component; begin RAM0: ramcell port map( din=>tb_din, dout=>tb_dout, addr=>tb_addr, ce=>tb_ce, rst_n=>tb_rst_n, clk=>tb_clk ); clkprocess:process is begin tb_clk <= '0'; wait for 5ns; tb_clk <='1'; wait for 5ns; end process clkprocess; tb_rst_n<='1' after 0ns,'0' after 1ns,'1' after 2ns; tb_ce<='0' after 0ns,'1' after 40ns,'0' after 90ns; tb_addr<=x"00" after 40ns,x"01" after 50ns,x"05" after 60ns,x"13" after 70ns,x"23" after 80ns,x"99" after 90ns,x"00" after 140ns,x"01" after 150ns,x"05" after 160ns,x"13" after 170ns,x"23" after 180ns,x"99" after 190ns; tb_din<=x"D00F" after 40ns,x"FACE" after 50ns,x"AFFE" after 60ns,x"DEAD" after 70ns,x"BEEF" after 80ns,x"1337" after 90ns; end architecture;