library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library std; use std.textio.all; entity romtab is port ( addr: in std_logic_vector(3 downto 0); data: out std_logic_vector(7 downto 0) ); end entity; architecture romtab_arch of romtab is signal debug: bit_vector(7 downto 0); begin with addr select data <= x"23" WHEN x"0", x"42" WHEN x"1", x"47" WHEN x"2", x"FF" WHEN others; process (addr) variable l: line; begin write(l,STRING'("hallo welt") ); write(l,TO_INTEGER(TO_UNSIGNED(addr))); writeline(output,l); end process; end architecture; use WORK.romtab; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity tb is end; architecture tb_arch of tb is signal tb_addr: std_logic_vector(3 downto 0); signal tb_data: std_logic_vector(7 downto 0); component romtab port ( addr: in std_logic_vector(3 downto 0); data: out std_logic_vector(7 downto 0) ); end component; begin R0: romtab port map(addr=>tb_addr,data=>tb_data); tb_addr<=x"0" after 0ns, x"1" after 1ns, x"2" after 2ns, x"3" after 4ns, x"0" after 10ns; end architecture;